1. Field of the Invention
The present invention relates to a data processing apparatus, and to a method for performing memory transactions within such a data processing apparatus.
2. Description of the Prior Art
Instruction sets provided for execution on the data processing apparatus, such as a processor core, will typically include a number of memory access instructions that, when executed, cause a memory transaction to be performed to move data between memory addresses in the memory address space and registers of a register file within the data processing apparatus. One type of memory access instruction is a store instruction used to store data from the register file to a specified memory address within the memory address space. Another example of a memory access instruction is a load instruction used to load data from a specified memory address in the memory address space into one or more registers of the register file.
The memory address space can be partitioned in a variety of ways, and hence whilst one or more portions of the memory address space may be reserved for actual memory, other portions of the memory address space may be associated with storage provided within devices other than memory. For example, a portion of the memory address space may be associated with storage within a display controller, another portion of the memory address space may be associated with storage within a universal asynchronous receiver/transmitter (UART) device used to translate data between parallel and serial forms (for example to allow serial communications over a computer or peripheral device serial port), etc.
Traditionally, a data processing apparatus such as a processor core would communicate with all of the devices associated with the memory address space via a single interface. Accordingly, within an integrated circuit containing the processor core, the processor core may have a single system interface for connecting the processor core to a system bus to which the various memory address space associated devices are also coupled.
More recently, it is known to provide a processor core with more than one interface via which communications with memory address space associated devices can be achieved. This hence allows the processor core to be coupled to different buses, employing different bus protocols. Memory accesses can then be directed via the appropriate interface, dependent on which bus the device being accessed is connected to.
Typically, different bus protocols have different characteristics, and hence by providing more than one bus, increased flexibility is provided with regard to how individual devices are coupled to the processor core, thereby for example allowing certain devices to be connected to a bus allowing higher throughput, whilst other devices are connected to a bus allowing higher latency, etc.
In systems where the processor core has more than one interface via which memory accesses can be performed, there have typically been two approaches for handling such memory accesses. In accordance with the first approach, the memory access instructions within the instruction set do not distinguish between the different interfaces being used, and hence any particular memory access instruction is executed in the same way, irrespective of which interface is being used to handle the required memory transaction for that memory access instruction. The separate interfaces then include the required circuitry to control performance of the memory transaction having regard to the relevant bus protocol. Hence, in such embodiments, the internal signals passing between the processing circuitry executing the memory access instruction and the relevant interface circuitry are identical irrespective of which interface circuitry is being used. This simplifies the operation of the processor core, but does not allow the processor core to take advantage of any of the performance benefits that may be associated with one of the interfaces. For example, if one of the interfaces is connected to a bus which can process memory transactions more quickly than the bus to which the other interface is connected, this performance benefit cannot be used to realise any performance benefit within the processor core itself, since the internal handling of the memory access instruction within the processor core is the same, irrespective of which interface is used.
An alternative approach which can be taken is to provide separate memory access instructions associated with the different interfaces. Hence, for a memory access to be performed via a first interface, a first type of memory access instruction may be used, whilst for an equivalent memory access to be performed via a second interface, a separate second type of memory access instruction may be used. Whilst this can allow the processor core to internally take advantage of any performance benefits that one interface may provide relative to the other interface, it significantly increases programming complexity, and hence is difficult to use in practice.
Accordingly, it would be desirable to provide an improved mechanism for performing memory transactions within a data processing apparatus, which allows the data processing apparatus to take advantage of performance benefits that may be available when using one interface, but without the requirement for separate memory access instructions to be provided within the instruction set in association with each memory interface.